TIA 1A - TELEVISION INTERFACE ADAPTOR (MODEL 1A)
8. Input ports
A. General Description
There are 6 input ports on this chip whose logic state may
be read on data line 7 with read addresses INPT0 through
INPT5. These 6 ports are divided into two types, "dumped"
and "latched". See Figure 8.
B. Dumped Input Ports (I0 through I3)
These 4 input ports are normally used to read paddle
position from an external potentiometer-capacitor circuit.
In order to discharge these capacitors each of these input
ports has a large transistor, which may be turned on
(grounding the input ports) by writing into bit 7 of the
register VBLANK. When this control bit is cleared the
potentiometers begin to recharge the capacitors and the
microprocessor measures the time required to detect a logic
1 at each input port.
As long as bit 7 of register VBLANK is zero, these four
ports are general purpose high impedance input ports. When
this bit is a 1 these ports are grounded.
These two input ports have latches which can be enabled or
disabled by writing into bit 6 of register VBLANK.
When disabled, these latches are removed from the circuit
completely and these ports become two general purpose input
ports, whose present logic state can be read directly by
When enabled, these latches will store negative (zero logic
level) signals appearing on these two input ports, and the
input port addresses will read the latches instead of the
When first enabled these latches will remain positive as
long as the input ports remain positive (logic one). A zero
input port signal will clear a latch value to zero, where
it will remain (even after the port returns positive) until
disabled. Both latches may be simultaneously disabled by
writing a zero into bit 6 of register VBLANK.