TIA 1A - TELEVISION INTERFACE ADAPTOR (MODEL 1A)
A hardware counter on this chip produces all horizontal
timing (such as sync, blank, burst) independent of the
microprocessor, This counter is driven from an external
3.58 Mhz oscillator and has a total count of 228. Blank is
decoded as 68 counts and sync and color burst as 16 counts.
There are one bit, addressable registers on this chip for
vertical sync and vertical blank. The timing for these
functions is established by the microprocessor by writing
zero or one into these bits. (VSYNC, VBLANK )
C. Composite Sync
Horizontal sync and the output of the vertical sync bit are
combined together to produce composite sync. This
composite sync signal drives a chip output pad to an
external composite video resistor network.
The 3.58 MHz oscillator also clocks a divide by three
counter on this chip whose output (1.19 Mhz) is buffered to
drive an output pad called 00. This pad provides the input
phase zero clock to the microprocessor which then produces
the system 02 clock (1.19 Mhz).
Software program loops require different lengths of time to
run depending on branch decisions made within the program.
Additional synchronization between the software and
hardware. This is done with a one bit latch called WSYNC
(wait for sync). When the microprocessor finishes a
routine such as loading registers for a horizontal line, or
computing new vertical locations during vertical blank, it
can address WSYNC, setting this latch high. When this
latch is high, it drives an output pad to zero connected to
the microprocessor ready line (RDY). A zero on this line
causes the microprocessor to halt and wait. As shown in
figure 2, WSYNC latch is automatically reset to zero by the
leading edge of the next horizontal blank timing signal,
releasing the RDY line, allowing the microprocessor to
begin its computation and register writing for this
horizontal television line or line pair.